This application claims the benefit of Korean Patent Application No. 2001-31020, filed on Jun. 2, 2001, the contents of which are herein incorporated by reference in their entirety.
FIG. 1 is a circuit diagram of a conventional data output buffer for an integrated circuit device. Referring to FIG. 1, the data output buffer includes a data transmission circuit 10, a pre-driver circuit 11, and an output driver circuit 17. The data transmission circuit 10 includes transmission gates T1 and T2, latch circuits 3 and 5, and inverters 1 and 7.
The transmission gate T1 outputs data DATA to the pre-driver circuit 11 in response to assertion (for example, to a logic xe2x80x9chighxe2x80x9d) of a transmission control signal BUF, and the transmission gate T2 outputs inverted data {overscore (DATA)} to the inverter 7 in response to assertion of the transmission control signal BUF.
The latch circuit 3, which includes inverters I1 and I2 connected in series, and the latch circuit 5, which includes inverters I3 and I4 connected in series, latch output signals of the transmission gates T1 and T2.
The pre-driver circuit 11 includes inverters 13 and 15, and the inverter 13 outputs a signal that swings between a first voltage (i.e., a first supply voltage) VDDP and a second voltage VSSP (i.e., a ground voltage) in response to the output signal of the transmission gate T1, and the inverter 15 outputs a signal that swings between the first voltage VDDP and the second voltage VSSP in response to an output signal of the inverter 7. In general, the first voltage VDDP is 3.3V or 2.5V, and the second voltage VSSP is a ground voltage.
The output driver circuit 17 includes a pull-up circuit MP1 and a pull-down circuit MN1. The pull-up circuit MP1 is implemented by a PMOS transistor MP1 and pulls up an output terminal OUT to a third voltage VDDQ (e.g., a second supply voltage) in response to an output signal UP of the inverter 13. The pull-down circuit MN1 is implemented by an NMOS transistor MN1 and pulls down the output terminal OUT to a fourth voltage VSSQ (e.g., a ground voltage) in response to an output signal DOWN of the inverter 15. Thus, the output terminal OUT swings between the third voltage VDDQ and the fourth voltage VSSQ.
In general, in order to reduce skew during transition to logic xe2x80x9chighxe2x80x9d or logic xe2x80x9clowxe2x80x9d of the signal at the output terminal OUT, xe2x80x9cturn-onxe2x80x9d resistance (hereinafter, referred to as xe2x80x9cRon_mp1xe2x80x9d) of the PMOS transistor MP1 and xe2x80x9cturn-onxe2x80x9d resistance (hereinafter, referred to as xe2x80x9cRon_mn1xe2x80x9d) of the NMOS transistor MN1 can be equalized by controlling the ratio of the channel length and the channel width of the PMOS transistor MP1 and the NMOS transistor MN1.
However, in a case where the third voltage VDDQ is lower than the first voltage VDDP, for example, in a case where the first voltage VDDP is 2.5V and the third voltage VDDQ is 1.8V, the xe2x80x9cturn-onxe2x80x9d voltage between the gate and the source of the PMOS transistor MP1 may be reduced, e.g., to 1.8V such that the xe2x80x9cturn-onxe2x80x9d resistance (Ron_mp1) of the PMOS transistor MP1 is undesirably high. However, the signal DOWN input to a gate of the NMOS transistor MN1 swings between the first voltage VDDP and the second voltage VSSP, and thus, the xe2x80x9cturn-onxe2x80x9d voltage between the gate and the source of the NMOS transistor MN1 is relatively high, even though the third voltage VDDQ is lower than the first voltage VDDP. As a result, a transition slope from logic xe2x80x9clowxe2x80x9d to logic xe2x80x9chighxe2x80x9d and a transition slope from logic xe2x80x9chighxe2x80x9d to logic xe2x80x9clowxe2x80x9d of the signal of the output terminal OUT become different, and thus, skew may occur in the signal at the output terminal OUT.
FIG. 2A illustrates output waveforms at the output terminal OUT in a case where the first voltage VDDP is the same as the third voltage VDDQ. In this case, xe2x80x9cturn-onxe2x80x9d resistance (Ron_mn1) of the NMOS transistor MN1 and xe2x80x9cturn-onxe2x80x9d resistance (Ron_mp1) of the PMOS transistor MP1 are the same. Thus, skew does not occur between the transition of the signal of the output terminal OUT from logic xe2x80x9clow (0V)xe2x80x9d to logic xe2x80x9chighxe2x80x9d OUT xe2x80x9cHxe2x80x9d and the transition from logic xe2x80x9chigh (2.5V)xe2x80x9d to logic xe2x80x9clowxe2x80x9d OUT xe2x80x9cLxe2x80x9d.
FIG. 2B illustrates output waveforms at the output terminal OUT in a case where the first voltage VDDP is different from the third voltage VDDQ. In this case, the xe2x80x9cturn-onxe2x80x9d resistance (Ronxe2x88x92mn1) of the NMOS transistor MN1 and the xe2x80x9cturn-onxe2x80x9d resistance (Ron_mp1) of the PMOS transistor MP1 are different. Thus, skew occurs between transition from logic xe2x80x9c0Vxe2x80x9d to logic xe2x80x9cOUT xe2x80x9cHxe2x80x9dxe2x80x9d and transition from logic xe2x80x9c1.8xe2x80x9d to logic xe2x80x9cOUT xe2x80x9cLxe2x80x9dxe2x80x9d.
According to some embodiments of the present invention, a data buffer circuit comprises first and second driver circuits operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to the first and second data signals. The data buffer circuit also comprises an output circuit comprising first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective ones of third and fourth voltages responsive to respective ones of the outputs of the first and second driver circuits. The data buffer circuit further comprises a transition compensation circuit operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal.
In some embodiments of the present invention, the transition compensation circuit comprises a driver circuit, e.g., an inverter, coupled in series with an input of one of the first and second driver circuits, and a bias control circuit coupled to a power supply input of the driver circuit and operative to vary an impedance between the power supply input and a power supply node responsive to the transition rate control signal. In further embodiments, the transition compensation circuit comprises a selective impedance reduction circuit operative to selectively provide an impedance in parallel with at least one of the first and second transistors of the output circuit responsive to the control signal. The data buffer circuit may also include a transition rate control signal generating circuit operative to generate the transition rate control signal responsive to, for example, a state of a fuse or comparison of one of the first and second voltages to a reference voltage.